1. Field of the Invention
The invention relates in general to switching converters used by integrated circuit (IC) testers for supplying power to IC devices under test, and in particular to a feedback compensated switching converter that minimizes variation in its output voltage under varying load conditions.
2. Description of Related Art
An IC tester supplies test signals to input terminals of an IC device under test (DUT) and monitors the DUT's output signals to determine whether they behave as expected. FIG. 1 depicts a typical prior art IC tester 10 including a host computer 12 communicating with a test head 14 via a computer bus 16. Before starting a test, host computer 12 sends program instructions to test head 14 via bus 16 defining the test signal patterns to be applied to DUT 18 during the test and indicating how the DUT output signals are expected to behave. During the test, test head 14 transmits test signals to input terminals of DUT 18, monitors DUT output signals and stores test data indicating whether the DUT output signals behave as expected. After the test, test head 14 forwards the test data to host computer 12 via bus 16.
A typical test head 14 includes a number (N>1) of printed circuit channel cards CH1 through CHN, each implementing one or more tester channels 20. Each tester channel 20 is connected to a separate pin of DUT for supplying a test signal input to the pin or for monitoring a DUT output signal appearing at the pin. A bus interface circuit 22 forwards instructions arriving from host computer 12 via bus 16 to channels 20 and forwards test results data from channels 20 to host computer 12 via bus 16.
A power bus 24 distributes a DC power supply signal VBUS produced by an off-line, AC-to-DC converter 26 to each channel card CH1 through CHN for powering components on the channel cards. The DC supply voltage VBUS will be relatively high, for example 48 volts DC, to limit the amount of current power bus 24 conveys, but each channel card CH1 through CHN includes an “intermediate bus converter” 28 for converting the 48VDC VBUS signal to a lower intermediate bus voltage VIB, such as for example 12 VDC. Since tester channels 20 require several (M>1) different supply voltages V1-VM for use as reference voltages and for powering the channels, a set of “point-of-use” converters 301 through 30M are provided on each channel card for converting the intermediate bus voltage VIB into the required supply voltages V1 through VM. Before the test, host computer 12 sends instructions via bus 16 and bus interface circuit 22 to each point-of-use converter 30 for setting each converter's output voltage.
Test head 14 also includes a power supply card 32 for converting the 48VDC VBUS signal into an output signal VOUT connected via signal path to the DUT's power input terminal, thereby producing a load voltage VDD between the DUT's power input terminal and ground. Power supply card 32 includes an intermediate bus converter 34 for converting the fixed bus voltage VBUS into a lower fixed intermediate bus voltage VIN, such as 12 VDC, and a compensated point-of-use switching converter 36 for converting the 12VDC VIN voltage into the output signal VOUT. A bus interface circuit 38 responds to an instruction from host computer 12 via bus 24 by supplying control data DREF to converter 36 indicating a desired set point voltage level VSP for the DUT load voltage VDD.
FIG. 2 models the load and feedback impedance of point-of-use converter 36 of FIG. 1 and shows that a signal path 44 having impedance 40 couples the output signal VOUT of converter 36 to DUT 18 to produce a load voltage VDD across load 41 of the DUT. Path impedance 40, which includes inductance, capacitance and resistance, filters VOUT so that the load voltage VDD appearing across DUT load 41 differs from VOUT, particularly when DUT load 41 draws a large current. The load voltage VDD can vary during a test because the amount of current DUT load 41 varies. Since test specifications typically require variations of the load voltage VDD from some specified set-point value VSP to be held within a specified range, converter 36 must compensate for variations in VDD. The load voltage VDD is therefore fed back to converter 36 via a separate feedback path 44 (FIG. 1) to enable converter 36 to monitor the load voltage and appropriately adjust its output voltage VDD to keep VDD as near as possible to VSP. Although the impedance 42 of feedback path 44 (FIG. 1) filters VDD so that the voltage of the feedback signal VFB converter 36 receives varies somewhat from VDD, the current of the feedback signal VFB is relatively small compared to the current of the VOUT signal so that the voltage of feedback signal VFB tracks the voltage of VDD much more closely than the voltage of VDD tracks that of VOUT. Thus converter 36 can monitor the DUT input signal voltage VDD by monitoring feedback signal VFB and can adjust VOUT as necessary to keep the voltage of VFB, and therefore the voltage of VDD, near its desired set point voltage VSP.
FIG. 3 depicts a typical prior art architecture for the compensating point-of-use converter 36 of FIGS. 1 and 2, including a digital-to-analog converter (DAC) 50, a feedback control circuit 52, a pulse-width modulator (PWM) 54, and a power converter 56 for converting the input signal VIN from intermediate bus converter 34 (FIG. 1) to the VOUT signal supplied to DUT 16. DAC 50 converts the DREF data from host computer 12 (FIG. 1) into a reference signal VREF of voltage matching the desired set point voltage VSP of VDD. Feedback control circuit 52 compares a filtered version of feedback signal VFB to VREF and produces a control signal VC for controlling PWM circuit 54 which produces a pulse-width-modulated output signal VPWM having a duty cycle D controlled by control signal VC. Power converter 56 responds to VPWM by producing the VOUT signal in response to the VIN signal from intermediate bus converter 34 of FIG. 1. The duty cycle D of VPWM controls the ratio VOUT/VIN.
FIG. 4 depicts an example implementation of power converter 56 of FIG. 3. When VPWM is high, transistor Q1 turns on to connect the VIN signal across a diode D1 and across a capacitor C1 via an inductor L1. Capacitor C1 charges, driving UP VOUT, which appears across capacitor C1. D1 is typically a FET biased ON, commonly referred to as a synchronous rectifier. When VPWM is low, VIN no longer charges C1 and VOUT falls. The average magnitude of VOUT is therefore a function of the duty cycle D of VPWM. This particular power converter, which produces an output voltage VOUT that is less than its input voltage, is called a “buck converter”.
FIG. 5 is a timing diagram depicting VPWM as a function of time. The VPWM signal is a square wave of period TP that is on for a time TON during each cycle. The ratio VOUT/VIN is equal to the duty cycle D=TON/TP of the VPWM signal, set by the voltage of control signal VC of FIG. 3. In the example buck converter circuit of FIG. 4VOUT/VIN=D. For other types of converter circuits known to those of skill in the art, the ratio VOUT/VIN can be a more complex function of D. For all power converters relying on pulse-width modulation, we can generally express VOUT/VIN as some function of duty cycle D:VOUT/VIN=f(D)For the buck converter of FIG. 4,f(D)=D For a typical “boost” converter producing an output voltage VOUT that is higher than its input voltage VIN,f(D)=1(1−D)For a typical “buck boost” converter producing an output voltage that can be either higher or lower than VIN f(D)=−D/(1−D)Other converters known to those of skill in the art, including for example sepic, flyback, forward, two-switch forward, active clamp forward, half bridge, push pull, full bridge, and phase shift converters, have output-to-input voltage ratios characterized by other functions of the duty cycle D of VPWM.
Referring again to FIG. 3, a typical feedback control circuit 52 will include an amplifier 36 and a pair of filters 38 and 40. The VREF signal output of DAC 50 drives a non-inverting input of amplifier 36. Filter 38 couples the VC signal to an inverting input of amplifier 32 while filter 40 couples VFB to the inverting input to amplifier 36. When designing feedback control circuit 52, those of skill in the art design filters 38 and 40 to optimize a selected combination of one or more converter performance criteria such as for example, audiosusceptibility, transient response, closed loop frequency response, noise immunity, and power dissipation. Such performance criteria depend to some extent on the duty cycle D of VPWM. A circuit designer will typically choose some nominal value of D, such as for example 0.5, and then design filters 38 and 40 to optimize a desired combination of performance criteria under the assumption that converter circuit 36 will operate at that particular duty cycle. During system operation the value of D will vary when the DUT load varies in order to keep VDD near the selected set point voltage VSP, but D will normally not vary over a wide range unless the load varies wildly. If the system is optimized for a value of D of 0.5, and the selected set point voltage VSP causes the value of D to remain close to 0.5, then the converter will exhibit close to optimum performance. However when the selected set point voltage VSP caused the value of D to reside in a range remote from 0.5, the converter will exhibit suboptimal performance. Generally the desired combination of performance criteria will be substantially optimal only for a narrow range of set point voltages and will be substantially less than optimal when the converter is set for any set point voltage outside that narrow range.
One way to resolve this problem is to provide filters 38 and 40 with adjustable transfer functions, and to appropriately adjust their transfer functions to optimize performance criteria for each selected value of VSP. However this approach increases the complexity of the filter design task, increases the cost and complexity of filters 38 and 40, and requires additional circuits for selecting and controlling the filter transfer functions.
What is needed is a converter for which a desired combination of performance criteria is optimized over its entire range of set point voltages without requiring filters having adjustable transfer functions.